This invention relates, in general, to packages for integrated circuits, and more particularly to high power surface mount lead frame packages with high pin counts.
Wafer fabrication innovations continue to increase circuit density per unit area on a semiconductor die. Higher circuit density per unit area generally corresponds to an increase in power dissipation, also increased circuit functionality generates higher input/output (I/O) pin counts. Both increased heat dissipation and higher pin counts are critical parameters which must be accommodated when designing a semiconductor package.
There are a myriad of semiconductor packages currently offered which meet the many criteria necessary for a high power application but most are high cost due to the expense or complications of manufacturing and materials. For example, a ceramic leaded chip carrier is a very common, high power, high pin count package which would be prohibitively expensive to house a semiconductor chip where cost is a key imperative. On the other end of the power package spectrum are thru hole power packages which use lead frame construction. This type of package is used for low cost circuits such as a voltage regulator. The lead frame thru hole package are lead limited (typically less than 20) which severely reduces the types of circuit applications it may accommodate.
Lead frame packages are well known in the semiconductor industry as low cost, simple to manufacture semiconductor packages, however, power dissipation is typically limited to one watt or less. It would be of great benefit if a low cost package could be developed capable of dissipating more than one watt and having greater than 20 leads for external connection.